The present invention relates to a CCD output signal generating circuit for generating a CCD output signal used in a solid state image pickup device or the like.
FIG. 1 shows a conventional CCD output signal generating circuit comprising a charge coupled device (CCD) type charge transfer device 10 used to transfer signal charges responsive to an input signal from an input signal source VIN in response to three-phase drive pulses .phi..sub.1 to .phi..sub.3 of a frequency f.sub.c of, for example, 7 to 14 MHz, and a signal processing circuit 20 to process an output signal from the charge transfer device 10. The charge transfer device 10 comprises a CCD register 11 to transfer the signal charges in response to the three-phase drive pulses .phi..sub.1 to .phi..sub.3, and, simultaneously, to transfer the signal charges to a floating diffusion region 13 through the region under an output gate 12 to which a predetermined DC voltage VD is applied, a reset gate 14 to which a reset pulse .phi..sub.R, synchronized with the drive pulses .phi..sub.1 to .phi..sub.3, is applied, and a drain region 15 to which a predetermined reset voltage VR is applied.
When the reset pulse .phi..sub.R is applied to the reset gate 14 in the charge transfer device 10, all signal charges in the floating diffusion region 13 flow into the drain region 15 through the region under the reset gate 14. In this instance, the potential of the floating diffusion region 13 is set to a reset level VR. Next, when the reset pulse .phi..sub.R is interrupted, the floating diffusion region 13 is disconnected from the drain region 15 so that the potential of the floating diffusion region 13 is set to a feed-through level. Thereafter, when the signal charges are led into the floating diffusion region 13 in response to the drive pulses .phi..sub.1 to .phi..sub.3, the floating diffusion region 13 is set to a potential corresponding to the amount of the signal charges. In this way, whenever the signal charges are time-sequentially transferred from the CCD register 11 into the floating diffusion region 13, the potential in the region 13 is sequentially set to the reset level VR, the feed-through level, and the signal level.
The signal processing circuit 20 comprises a source follower circuit or output circuit 21 which is constituted by a MOS transistor TR1, and which receives, at its gate, the voltage corresponding to the signal charges accumulated in the floating diffusion region 13, a load MOS transistor TR2 in which one end is connected to a power source terminal VB through the MOS transistor TR1 and the other end is grounded, and a correlated double sampling circuit 22 to eliminate the reset noise from the output signal of the output circuit 21. The MOS transistor TR2 can be used as a resistive element.
The output circuit 21 generates an output signal, shown in FIG. 2, in response to the voltage corresponding to the signal charges accumulated in the floating diffusion region 13. Specifically, when the potential of the region 13 is set to the reset level, feed-through level and signal level, respectively, the output signal is, similarly, set to accord with the reset level, feed-through level and signal level, respectively, for a reset period RSP, a feed-through level set period RVP and a signal level set period SVP.
In the voltage waveform shown in FIG. 2, a differential voltage A between the reset voltage for the reset period RSP and the feed-through voltage for the feed-through level set period RVP, is a synchronous noise synchronized with the resetting operation. A differential voltage B between the feed-through voltage and the signal voltage for the signal level set period SVP, is an output signal voltage corresponding to the signal charges in the floating diffusion region 13. Since the frequency of the synchronous noise is equal to the frequency f.sub.c of the drive pulses .phi..sub.1 to .phi..sub.3 of the CCD register 11, by coupling a low-pass filter, having a cut-off frequency of 1/2 f.sub.c, with an output terminal of the output circuit 21, this synchronous noise can be eliminated.
In addition to this synchronous noise, two further kinds of noises are mixed into the output signal of the output circuit 21. One noise is caused due to the thermal noise generated in an ON resistance in the region under the reset gate 14 when the reset pulse .phi..sub.R is applied to the reset gate 14. The feed-through level for the feed-through level set period RVP varies at every cycle and appears as a reset noise .DELTA.B as shown in FIG. 2. The other noise is the noise generated in the output circuit 21.
To suppress the above-mentioned reset noise, the correlated double sampling circuit 22 is ordinarily connected to the output terminal of the output circuit 21. The correlated double sampling circuit 22 detects the difference B between the reference voltage level and the signal voltage level in each operation cycle and generates an output signal corresponding to the difference B. As described above, since the correlated double sampling circuit 22 generates the output signal corresponding to the difference B, it is possible to generate an output signal that is not influenced by the synchronous noise A shown in FIG. 2.
For example, as shown in FIG. 3, the correlated double sampling circuit 22 comprises a clamping circuit 220 to clamp the reference voltage in the output signal from the output circuit 21, at a predetermined level, a buffer amplifier BA1 to amplify an output voltage of the clamping circuit 220, a sample-hold circuit 230 to sample and hold an output voltage from the buffer amplifier BA1 during the foregoing signal voltage set period, and a buffer amplifier BA2 to amplify an output voltage from the sample-hold circuit 230. The clamping circuit 220 has a DC-cut capacitor C1 connected between the output circuit 21 and the amplifier BA1, and a switch SW1, turned on during the reference voltage set period, which is connected between an input terminal of the amplifier BA1 and the ground. The sample-hold circuit 230 includes a switch SW2 which is connected between the amplifiers BA1 and BA2 and turned on during the signal voltage set period, and a capacitor C2 connected between an input terminal of the amplifier BA2 and the ground.
As described above, by processing the output signal from the output circuit 21 by the correlated double sampling circuit 22, it is possible to derive an output signal, which is not influenced by the synchronous noise and reset noise included in the output signal, from the output circuit 21, the output signal corresponding to the signal charges accumulated in the floating diffusion region 13. However, the noises generated in the output circuit 21 can hardly be eliminated because of the alias of the high frequency noise, that is the reflection of the high frequency noise into the low frequency range.
The alias of the high frequency noise will now be described with reference to FIGS. 4A and 4B.
FIG. 4A shows, schematically, an example of the spectrum of the noises included in the output signal of the output circuit 21. The CCD output signal component from the output circuit 21 exists within a frequency range lower than 0.5 f.sub.c. Thus, in the case where the correlated double sampling circuit 22 is not used, this CCD output signal component is only affected by the noise component NA of a frequency lower than 0.5 f.sub.c. It is possible to ignore the influence of the noise components NB, NC, ND . . . , with frequencies between (2n-1)f.sub.c /2 and (2n+1)f.sub.c /2 (n is a positive integer).
In contrast, by use of the correlated double sampling circuit 22, the noise component NA below 0.5 f.sub.c, which is included in the output signal from the output circuit 22, is largely suppressed, as shown by the noise component NA.sub.1 in FIG. 4B. At the same time, the other noise components NB, NC, ND . . . , are also suppressed in the respective corresponding frequency ranges, as indicated by the noise components NB.sub.2, NC.sub.2, ND.sub.2 . . . . However, in this case, parts of the noises NB, NC, ND . . . , in the high frequency region, are aliased or reflected in the frequency range below 0.5 f.sub.c, so that the noise components NB.sub.1, NC.sub.1, ND.sub.1, corresponding to the noise components NB, NC, ND . . . , could have been generated in the frequency range below 0.5 f.sub.c. Thus, there is a possibility that such noise components in the frequency region below 0.5 f.sub.c, which are included in the output signal from the correlated double sampling circuit 22, will become larger than the noise components in the frequency range below 0.5 f.sub.c, which are included in the output signal of the output circuit 21. Specifically, therefore, when the correlated double sampling circuit 22 is used, the synchronous noise can be eliminated and the reset noise suppressed, but the noises generated in the output circuit 21 can be neither eliminated nor suppressed.